The present invention relates, in general, to the field of semiconductor integrated circuit devices. More particularly, the present invention relates to a data bus charge-sharing technique for integrated circuit devices.
An integrated circuit device having a large number of internal data buses can have high power dissipation due to the data buses switching at high frequency. One way to reduce this power is to reduce the voltage swing on the data buses to a fraction of the power supply voltage, VCC. There are various ways to do this.
To further reduce power it is desirable to share charge between two or more sets of data buses. Conventional implementations of this technique have involved stacking circuits and/or data buses between the VCC and ground, where the highest voltage level of signals in one set of circuits and/or data buses is equal to the lowest voltage level of signals in another set of circuits and/or data buses. This scheme effectively shares charge between the two sets of circuits and/or data buses.
A novel and efficacious charge-sharing technique is disclosed in the aforementioned patent application. Utilizing this technique, charge is shared between two sets of small signal differential precharged data buses. One set of data buses switches between VCC and approximately 0.9 times VCC and the other set of data buses switches between 0.1 times VCC and 0V. In this case the lowest voltage level of one set of data buses is not set equal to the highest voltage level of the second set of data buses. Therefore, new methods of charge-sharing must be utilized.
In this previously referenced patent application, a switched capacitor circuit is disclosed as one means for providing the charge-sharing function. In this case, charge used to drive data lines from VCC to 0.9 times VCC in one set of data buses is also used to drive data lines from 0V to 0.1 times VCC in the second set of data buses. This charge is transferred, in the preferred embodiment, through the switched capacitors.
In the implementation of the particular technique disclosed in the previously filed patent application, the internal voltage levels, 0.9 times VCC and 0.1 times VCC, are determined by the relative capacitances on the two sets of data buses and the switched capacitor. Since this may possibly lead to some uncertainty in establishing these voltage levels, it could also result in increased power and/or insufficient signal levels. Moreover, this particular technique is most particularly applicable for differential precharged data buses and additional circuitry may be required to ensure reliable low frequency operation.